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Our early report The Custom AI Silicon Era | Jarsy Research #22 mapped the companies and architectures challenging GPUs in AI computing. SambaNova stood out for building an integrated platform spanning dataflow processors, memory, software and rack-scale systems.
Founded in 2017 from Stanford research, SambaNova developed a software-controlled, reconfigurable architecture supported by its own compiler, software and complete systems. After initially focusing on model training, the company shifted towards inference and entered 2026 with its fifth-generation SN50 processor, major customers and a closer relationship with Intel. In July, it announced the first close of a $1 billion Series F at an $11 billion post-money valuation. This report examines SambaNova’s founders, technology and products and whether its ambitious, capital-intensive platform can become a durable business.
1. From Stanford Research to SambaNova
SambaNova began at the intersection of two long-running partnerships. At Stanford, professors Kunle Olukotun and Christopher Ré brought complementary perspectives to AI computing. Olukotun specialized in parallel processors and programming models, while Ré focused on machine learning, databases and data-intensive software. Their work raised a compelling question: what if hardware could be configured around the computational graph of a model, rather than forcing the model to conform to a conventional processor?
Olukotun knew someone who could help turn that research into silicon. Rodrigo Liang had been director of engineering at Afara Websystems, the multicore-processor startup Olukotun founded in 2000 and sold to Sun Microsystems two years later. Liang subsequently led major processor-development teams at Sun and Oracle. He brought something the academic project still lacked: experience taking an unconventional architecture from an idea to a commercial product.
The three founded SambaNova in 2017. Olukotun provided the architectural foundation, Ré connected it to machine-learning software and Liang became CEO, charged with building the company and bringing its technology to market. Semiconductor investor Lip-Bu Tan soon joined the story: Walden International and GV co-led SambaNova’s $56 million Series A in 2018, when Tan became chairman. He moved into the executive-chairman role in 2024, adding his experience from Cadence and the wider semiconductor industry.
Kunle Olukotun, Rodrigo Liang and Christopher Ré. Image credits: SambaNova
SambaNova initially targeted organizations running demanding machine-learning and data-analytics workloads. But it kept evolving: it launched its first commercial system in 2020, introduced successive generations of RDU hardware and shifted towards cloud-first inference in 2025. The timeline below traces that development:
Figure 1. Selected milestones in SambaNova’s development. Sources: SambaNova; Reuters; EE Times; Business Wire. © 2026 Jarsy Research
2. From RDU to SambaStack: Building the Complete System
SambaNova’s offering extends from processors to complete AI services. The Reconfigurable Dataflow Unit (RDU) is its core processor technology; SambaRack combines multiple RDUs with memory, networking and servers; and SambaStack adds the software needed to operate dedicated AI infrastructure. Customers can also access the technology through SambaCloud, or use SambaManaged to launch a locally hosted inference service operated with SambaNova.
SambaNova RDUs (left) and SambaRack (right). Image credits: SambaNova
2.1 From parallel patterns to the RDU
The RDU’s intellectual roots can be traced to Stanford’s 2017 Plasticine research. Instead of beginning with a conventional processor, the researchers identified recurring patterns of parallel computation and derived the compute, memory and communication resources needed to execute them efficiently.
SambaNova later described this principle through patterns such as Map, Zip and Reduce, which capture both computation and data movement. SambaFlow (SambaNova’s software system) analyses those relationships and configures the RDU’s compute units, memory units and interconnects around the resulting graph.
Figure 2: Example Parallel Patterns - Map, Zip and Reduce. Source: SambaNova White Paper
2.2 The science of dataflow
An AI model can be represented as a computational graph: one operation produces data consumed by the next. Conventional processors commonly execute sections of that graph as separate kernels. Between kernels, intermediate results may be synchronized, written to memory and loaded again. The arithmetic may be fast while the system waits for data.
Consider a simplified neural-network layer:
y=ReLU(Wx+b)
It combines matrix multiplication, addition and activation. A kernel-based processor may execute and store each operation separately; an RDU maps them onto connected resources that operate as a pipeline. Once filled, several stages run concurrently, reducing synchronization and intermediate data movement without changing the underlying mathematics.
Table 1: RDU vs Conventional execution. © 2026 Jarsy Research
2.3 Inside the RDU: SN40L as an Example
Each SN40L contains a reconfigurable grid of four main components:
Pattern Compute Units (PCUs) perform matrix multiplication, vector arithmetic, element-wise operations and reductions. They can be configured as systolic arrays or multistage SIMD pipelines.
Pattern Memory Units (PMUs) combine distributed SRAM with addressing and data-management functions, keeping inputs, parameters and intermediate results close to the compute units.
Address Generation and Coalescing Units (AGCUs) organize memory requests and support regular and irregular tensor-access patterns.
The Reconfigurable Dataflow Network (RDN) moves data between the PCUs, PMUs and AGCUs through a two-dimensional mesh.
SambaFlow maps an AI model onto these resources, deciding where each operation runs, where its data is stored and how results move to the next stage. Multiple operations can therefore be fused into longer pipelines, allowing intermediate results to remain on-chip instead of repeatedly travelling to external memory.
PMUs and PCUs. Image Credit: SambaNova
The SN40L combines 1,040 PCUs and 1,040 PMUs with distributed SRAM and two larger memory tiers. Its architecture also enables compiler optimizations such as “kernel looping,” which reduced synchronization between repeated decoder layers and accelerated decoding by up to 2.2 times compared with the same SN40L hardware without the optimization.
2.4 Memory is part of the architecture
Large models cannot fit entirely inside the RDU’s on-chip memory. SN40L therefore combines three memory tiers:
Figure 3: SN40L Three-Tier Memory System. Source: SambaNova. © 2026 Jarsy Research
The relevant constraint can be summarized by the Roofline relationship:
Performance ≤ min (Peak compute, Memory bandwidth × Arithmetic intensity)
Arithmetic intensity measures how much computation is performed for each byte moved from memory. When a workload becomes memory-bound, adding more arithmetic units produces little benefit unless data can reach them faster. SambaNova’s compiler and runtime therefore manage which data stays in SRAM, which remains in HBM and which can be stored in larger DDR memory. This is particularly relevant to inference, where generating each token requires repeated access to model weights and the KV cache.
2.5 From SN40L to SN50
The fourth-generation SN40L is SambaNova’s technically documented and commercially deployed processor. The fifth-generation SN50, announced in February 2026, retains the dataflow architecture and tiered-memory approach but focuses more directly on agentic inference, particularly decoding, prompt caching and frequent switching among models. SambaNova says SN50 also offers four times SN40’s network bandwidth and can hot-swap models in milliseconds, but has not disclosed the underlying specifications.
Table 2: SN40L vs SN50. Source: SambaNova. © 2026 Jarsy Research
2.6 From RDU to Customer Deployment
SambaNova offers three principal ways to deploy its technology. SambaStack combines dedicated hardware and software inside a customer’s datacentre, while SambaCloud provides hosted access through an API. SambaManaged enables organizations to launch locally hosted AI services with SambaNova helping to deploy and operate the infrastructure.
Underneath these options is SambaRack, the physical system containing 16 RDUs alongside memory, networking and servers. Customers can connect multiple racks when larger models or greater inference capacity require more resources. Together, these models allow SambaNova to serve customers that want direct control of their infrastructure as well as those that prefer a hosted or managed service.
Table 3: SambaNova’s products. © 2026 Jarsy Research
3. Main Customers and Use cases
SambaNova’s strongest market is not simply organizations looking for a faster AI processor. It is customers that need to run advanced models but face practical constraints around power, data sovereignty, deployment time or infrastructure complexity.
Table 4: SambaNova’s main customers. © 2026 Jarsy Research
Deployment of SambaNova Suite in Argonne National Laboratory. Image Credit: Argonne National Laboratory
The appeal changes with the customer. Sovereign providers and regulated enterprises gain control over where their data and models reside. Datacentre operators can add inference capacity using air-cooled systems designed for existing facilities. Inference providers receive a complete platform for serving large or multiple models, while developers can access the same architecture through SambaCloud without operating the hardware themselves.
This range illustrates the commercial logic behind SambaNova’s full-stack strategy: rather than asking every customer to adopt a new chip directly, the company packages its architecture as private infrastructure, managed deployments and cloud services.
4. Competition and Capital
SambaNova competes with broad GPU platforms as well as processors designed specifically for inference. Its position rests on three features: reconfigurable dataflow, three-tier memory and complete air-cooled systems for private or sovereign deployment.
4.1 The competitive field
Nvidia remains the main commercial threat because it competes at every level: processor, networking, software and rack. Groq, Cerebras and d-Matrix are closer architectural comparisons, each sacrificing some flexibility to improve inference performance. Etched is the most direct emerging comparison to SambaNova’s full-system strategy, but remains earlier in commercialization.
Table 5: SambaNova’s main competition. Sources: Nvidia, AMD, Groq, Cerebras, d-Matrix, Etched, Google. © 2026 Jarsy Research
SambaNova occupies a middle ground. It is more specialized than a GPU but more adaptable than a fixed inference ASIC. Its tiered memory allows it to hold large or multiple models without relying entirely on expensive SRAM, while its air-cooled racks fit datacentres that cannot accommodate the power and cooling requirements of the densest GPU systems. The trade-off is adoption risk: customers must accept a smaller software ecosystem, fewer publicly documented deployments and greater dependence on a single private supplier.
4.2 Funding and valuation
SambaNova’s full-stack strategy has required substantial capital. Its investors have expanded from early technology funds to global institutions as the company moved from research to commercial deployment.
Table 6: SambaNova’s funding rounds. Sources: CNBC, Sacra, SambaNova. © 2026 Jarsy Research
These disclosed rounds total more than $2.48 billion. The reported valuation rose from about $2.5 billion in 2020 to more than $5 billion in 2021, then reached $11 billion post-money in July 2026.
Intel is the most strategically important recurring investor, with an approximately 8.2% stake, a multiyear commercial partnership and CEO Lip-Bu Tan serving as SambaNova’s executive chairman. The latest valuation reflects confidence in SambaNova’s inference strategy; the next test is turning SN50 and its major customer announcements into sustained deployments.
5. What Comes Next
Beyond SN50, SambaNova is exploring disaggregated inference, assigning compute-heavy prefill to GPUs and memory-bound decode to RDUs. In June 2026, the company demonstrated Nvidia B200 GPUs working with SN40 RDUs at Vector Core Compute, naming Together AI as the first commercial customer. The project suggests that RDUs may increasingly work alongside GPUs rather than replace them across every workload.
SambaNova separates inference across GPUs for prefill and RDUs for decode. Image credit: SambaNova.
The near-term test is shipping SN50, scaling it across multiple racks and turning announced partnerships into sustained production deployments. As explored in our research Inside Etched: The Transformer-First Inference Bet, AI-chip startups are taking different approaches to specialization. Etched is designing an integrated system for both prefill and decode; SambaNova combines reconfigurable hardware with systems that can assign each stage to a different processor.
SambaNova’s future rests on whether reconfigurability proves to be a meaningful middle ground: more efficient than general-purpose GPUs, but adaptable enough to keep pace with a rapidly changing model landscape. Whether it can turn that middle ground into a durable market position is now the question to watch.
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